Title :
A design methodology for modelling CMOS gates based on Petri nets
Author :
Hadjinicolaou, M.G.
Author_Institution :
Dept. of Electr. Eng. & Electron., Brunel Univ. of West London, Uxbridge, UK
Abstract :
A design methodology for deriving switch level equivalent circuits for CMOS combinational logic circuits based on Petri nets is presented. Detailed Petri net models of the p- and n-type transistors are discussed, and the use of these models to construct the CMOS gates (i.e., NOT, NAND, NOR) for logic correctness is illustrated. How the proposed methodology can be extended to include timing verification is discussed
Keywords :
CMOS integrated circuits; Petri nets; combinatorial circuits; equivalent circuits; logic circuits; logic design; logic gates; CMOS gates modelling; NAND-gates; NOR-gates; NOT-gates; Petri net models; Petri nets; combinational logic circuits; design methodology; logic correctness; n-type transistors; p-type transistors; switch level equivalent circuits; timing verification; CMOS logic circuits; Circuit simulation; Combinational circuits; Design methodology; Equivalent circuits; Petri nets; Semiconductor device modeling; Switches; Switching circuits; Timing;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.251966
