Performance and dependability of gracefully-degradable multiprocessor systems

The author presents an analytical model for dependability and performance evaluation of a multiprocessor system containing P processors, M memories, and B buses. The system is gracefully degradable and the main memory is M-way interleaved. In case of a fault the reconfiguration scheme will arrange the nonfaulty modules into groups, and the bus assignment to each group is made according to the increase in the number of modules per group. An expression for the mean amount of bandwidth available on the system at a certain time considering the online maintenance is obtained. Online system availability is also discussed, and a relation is developed. Expressions for the offline maintenance policies are obtained by considering the situations where the system has failed due to the exhaustion of the processors or memory modules or due to buses