Self-timed design: An avenue to complex computer systems

Asynchronism could prove to be the way to build huge systems, except for incoming hazards. This paper introduces an original methodology for hazard-free self-timed design, assuming the worst conditions for robustness. Hazards are classified under three types. On top of logic hazards that resort to implementation, equation hazards are eliminated by an optimal covering. A new variable, labeled state trajectory is proposed: its integrity guarantees immunity to function hazards. The method was fruitfully applied to the VLSI CMOS implementation of a router for a parallel machine. Peculiar full-custom cells are designed. The measured performances of the circuit are presented, as well as some more global machine performances for communication.