An improved model for SOI enhancement and depletion JFETs with nonuniform channel parameters for low/high-speed applications

The dynamic operation of various n-channel silicon-on-insulator (SOI) junction field effect transistors (JETs) is presented. A previously developed program, based on an accurate model of the SOI JFET I-V characteristics, taking into account the effect of SOI structure on the charge carrier mobility, is modified to include the calculations of the device parameters and high-speed figures of merit. The authors present the DC, AC, and transient response analysis of inverters with n-channel E-JFET drivers and depletion-type loads. (E/D inverters). Results are simulated for different device parameters and supply voltages for VLSI circuit applications. A fifteen-stage ring oscillator is used to rate the performance of the SOI E/D JFET inverters for future digital logic applications. SOI E/D inverter performance compared favorably with typical GaAs inverter structures