A diffused CMOS SRAM compiler for gate-arrays

Author

Gee, Perry ; Tou, Jarvis

Author_Institution

Motorola Inc., Chandler, AZ, USA

fYear

1991

fDate

14-17 May 1991

Firstpage

807

Abstract

The authors present a highly configurable embedded SRAM (static random-access memory) compiler that can generate both single and dual-port diffused SRAMs. The synthesis of these RAMs does not require any engineering intervention or knowledge of SRAM design. The compiler allows one to make accuracy vs. time tradeoffs in SRAM characterization by offering three different simulation methodologies

Keywords

CMOS integrated circuits; SRAM chips; application specific integrated circuits; circuit layout CAD; logic CAD; logic arrays; SRAM characterization; SRAM design; configurable embedded SRAM; diffused CMOS SRAM; dual-port diffused SRAMs; gate-arrays; simulation methodologies; single port SRAMs; static RAM compiler; static random-access memory; synthesis technique; Application specific integrated circuits; Automatic testing; Character generation; Costs; Design engineering; Libraries; Packaging; Random access memory; Read-write memory; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-0620-1

Type

conf

DOI

10.1109/MWSCAS.1991.251990

Filename

251990

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3398085