Clock controlled Hybrid-latch flip-flops design

Author

Jia Song ; Yan Shilin ; Wu Fengfeng ; Wang Yuan

Author_Institution

Key Lab. of Microelectron. Devices & Circuits (MOE), Peking Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

In order to obtain power efficient flip-flops, two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inverter chain pulse generator. HSPCE simulation under SMIC 90nm process revealed that the two new flip-flop have excellent power and speed performance compared to the referenced design. They can reduce 44.5% and 51.4% power dissipation, 29.2%and 44.5% clock-to-output latency and 65.6% and 68.4% PDP.

Keywords

clocks; flip-flops; logic design; HSPCE simulation; SMIC process; clock controlled hybrid-latch flip-flops design; clock-to-output latency; critical data path shortening; efficiency 29.2 percent; efficiency 44.5 percent; efficiency 51.4 percent; efficiency 65.6 percent; efficiency 68.4 percent; hybrid-latch scheme; inverter chain pulse generator elimination; power dissipation; power efficiency; Clocks; Delay; Flip-flops; Inverters; Latches; Transistors; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466686

Filename

6466686