Title :
Design tools for 3-D integrated circuits
Author :
Das, Shamik ; Chandrakasan, Anantha ; Reif, Rafael
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
We present a set of design tools for 3-D integration. Using these tools - a 3-D standard-cell placement tool, global routing tool, and layout editor - we have targeted existing standard-cell circuit netlists for fabrication using wafer bonding. We have analyzed the performance of several circuits using these tools and find that 3-D integration provides significant benefits. For example, relative to single-die placement, we observe on average 28% to 51% reduction in total wire length.
Keywords :
VLSI; application specific integrated circuits; cellular arrays; circuit layout CAD; integrated circuit layout; network routing; 3D IC design tools; 3D integrated circuits; 3D integration; 3D standard-cell placement tool; global routing tool; layout editor; standard-cell circuit netlists; wafer bonding; Coupling circuits; Delay; Fabrication; Integrated circuit interconnections; Partitioning algorithms; Performance analysis; Three-dimensional integrated circuits; Transistors; Wafer bonding; Wire;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1194993
