DocumentCode :
3398648
Title :
Algorithms for compacting error traces
Author :
Chen, Yirng-An ; Chen, Fang-Sung
Author_Institution :
Novas Software Inc., San Jose, CA, USA
fYear :
2003
fDate :
21-24 Jan. 2003
Firstpage :
99
Lastpage :
103
Abstract :
In this paper, we present a concept of compacting the error traces generated by pseudo-random/random simulations. The new shorter error trace not only decreases the time of the user´s debugging process but also reduces the simulation time required to verify the bug fixes. Two algorithms, CET1 and CET2, are presented to perform the task of compacting the error trace. Both algorithms first use an efficient approach to eliminate the redundant states, to generate the unique states of the error trace. Then, CET1 builds the connected graph of these unique states by computing the reachable states by one cycle for each unique state, and then applies Dykstra´s shortest path algorithm to find out the shortest error trace in the connected graph. Compared with CET1, CET2 computes the reachable states by one cycle for those unique states, when they are needed in Dykstra´s shortest path algorithm to find the shortest error trace. After finding the shorter trace, the corresponding input/output test vectors are generated. The experimental results show that both algorithms can reduce the length of error traces dramatically for most cases using reasonable memory. For cases requiring longer CPU time to find the shortest trace, CET2 is up to 37 times faster than CET1.
Keywords :
circuit simulation; error detection; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; Dykstra shortest path algorithm; bug fix verification; debugging process time reduction; error trace compacting algorithms; error trace compaction; error trace length reduction; input/output test vectors; one cycle reachable states; pseudo-random simulation; random simulation; redundant state elimination; shortest error trace computation; unique error trace states; unique state connected graph; Circuit simulation; Computer bugs; Contracts; Councils; Debugging; Digital circuits; Power capacitors; Silicon; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
Type :
conf
DOI :
10.1109/ASPDAC.2003.1195000
Filename :
1195000
Link To Document :
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