Title :
Selective parallel CRC computation schemes for RapidIO
Author :
Wu Fengfeng ; Jia Song ; Xu Heqing ; Wang Yuan ; Zhang DaCheng
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits (MOE), Peking Univ., Beijing, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
RapidIO is a high-performance standard for embedded interconnections. Due to different ending alignments of RapidIO packets, the corresponding CRC computations should be adjustable. In this paper, two selective parallel computation schemes based on simplified intermediate value equations are proposed. Compared with the reference designs, the power dissipations can be reduced by more than 30% meanwhile better balances between the speeds and resource consumptions can be achieved.
Keywords :
cyclic redundancy check codes; embedded systems; interconnections; RapidIO packet standard; embedded interconnection; power dissipation; resource consumption; selective parallel CRC computation scheme; simplified intermediate value equation; speed consumption; Cyclic redundancy check codes; Mathematical model; Polynomials; Power dissipation; Registers; Table lookup;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6466703
