Power optimization in a 16-bit 200 MSPS pipeline ADC

In this paper, the power analysis and optimization for the high-speed high-resolution pipeline ADC´s are presented. The dependency of the power dissipation on the speed, the resolution, the SNR, the power supply, the effective stage resolutions of the ADC, the scaling index of the sampling capacitors, and the compensation capacitors of the residue amplifier are discussed. The great influence of comparator capacitors on the optimization of high-speed high-resolution ADC´s is demonstrated. The low-power design technique on systematic level is presented and applied to a 16-bit 200MSPS pipeline ADC. Simulation confirms that the ADC shows more than 71dB of SNR for a 99.9MHz input at 2Vpp at full sampling rate and the ADC core consumes less than 700mW from a 1.8V supply of a 0.18um CMOS process.