Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

This paper proposes a rapid evaluation scheme of pipeline architectures using phase-accurate simulation with only delay model and trace. With latency information for every stage, we can decide if an instruction in one stage can proceed to the next stage or if an instruction can be issued for each cycle without evaluating the value for registers. Branch target becomes available with trace generated by fast instruction set simulation. Fast verification time becomes possible because instruction set simulation is performed only once.