DocumentCode
3398795
Title
High voltage low side and high side power devices based on VLD technique
Author
Mou-fu Kong ; Xing-bi Chen
Author_Institution
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
Based on PN junction isolation and VLD techniques, high voltage low side and high side power LDMOS transistors are presented. The solution is compatible with CMOS process and BiCMOS process, and the devices are analyzed and confirmed by simulation.
Keywords
BiCMOS integrated circuits; CMOS integrated circuits; p-n junctions; power MOSFET; BiCMOS process; PN junction isolation; VLD technique; high voltage high side power devices; high voltage low side power devices; power LDMOS transistors; Breakdown voltage; Doping; Integrated circuits; Junctions; Simulation; Transistors; Voltage control; Junction isolation; LDMOS; Power devices; VLD;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6466709
Filename
6466709
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