Physically based description of quasi-saturation region of vertical DMOS power transistors

Author

Kreuzer, C.H. ; Krischke, N. ; Nance, P.

Author_Institution

Bundeswehr Univ., Munich, Germany

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

489

Lastpage

492

Abstract

For short circuit design protection, quasi-saturation behaviour of vertical power DMOS transistors has to be included in circuit simulator compact models. In this region an unexpected increase in current has been observed, due to the injection of electrons from the n/sup +/ source region into the n-substrate. The purpose of this paper is to analyze this effect and include its results in a compact model for circuit simulation.

Keywords

circuit analysis computing; electric resistance; electron density; power MOSFET; semiconductor device models; voltage distribution; circuit simulation; circuit simulator compact models; drain resistance; electron concentration; electron injection; n-substrate; n/sup +/ source region; physically based description; quasi-saturation region; short circuit design protection; vertical DMOS power transistors; voltage distribution; Analytical models; Circuit simulation; Contact resistance; Doping; Electric resistance; Electron mobility; Immune system; Medical simulation; Power transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553844

Filename

553844