Design of low logical cost adders using novel Parity Conserving Toffoli Gate

Reversible Logic has turned out to be one of the promising computing technologies assuring zero power dissipation. It has a wide spectrum of applications like Low Power VLSI, quantum computing, Bio Informatics, Optical Circuits and Nanotechnology based systems. It also addresses the issues of Fault tolerance through a special class of gates called parity preserving reversible logic gates. This paper aims to design a fault tolerant full adder using the new Parity Conserving Toffoli Gate, which can in turn be employed to construct ripple carry adders, and other high speed adders. The design has the most optimized performance parameters than its counterparts that are studied in the literature.