Title :
A technology mapping algorithm for heterogeneous FPGAs
Author :
Kao, Chi-Chou ; Lai, Yen-Tai
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
In this paper, a technology mapping algorithm is proposed for heterogeneous FPGAs. The technology mapping problem is first formulated as a flow network problem. Then, an algorithm based on the min-cost max-flow algorithm is presented to select a proper set of feasible LUTs for various objectives. The objective, the total area composed of LUTs and routing area, are discussed in the paper. This algorithm has been tested on the MCNC benchmark circuits. Compared with other existing LUT-based FPGA mapping algorithms, the algorithm produces better characteristics.
Keywords :
CMOS logic circuits; circuit CAD; circuit layout CAD; circuit optimisation; directed graphs; field programmable gate arrays; high level synthesis; integrated circuit design; minimax techniques; network routing; table lookup; CMOS technology; LUT-based mapping algorithm; flow network problem; heterogeneous FPGAs; lookup table based FPGA device; min-cost max-flow algorithm; technology mapping algorithm; Benchmark testing; Circuit testing; Combinational circuits; Equivalent circuits; Field programmable gate arrays; Logic devices; Logic gates; Routing; Table lookup; Terminology;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195019
