Title :
Implementation of pipelined sobel edge detection algorithm on FPGA for High speed applications
Author :
Vanishree ; Reddy, K. V. Ramana
Author_Institution :
VTU Extension Center, UTL Tech. Ltd., Bangalore, India
Abstract :
In this paper we present Implementation of pipelined Sobel edge detection algorithm on FPGA for High speed applications. An optimized Gradient-based edge detection method which reduces the delay by around 50% when compared to the standard architecture has been proposed in this paper. The algorithm is implemented on Spartan 3E FPGA board. The Video Graphics Array (VGA) is developed to interface the FPGA to the monitor to display the edge detected image.
Keywords :
edge detection; field programmable gate arrays; gradient methods; Spartan 3E FPGA board; VGA; high speed applications; optimized gradient-based edge detection method; pipelined sobel edge detection algorithm; video graphics array; Algorithm design and analysis; Computer architecture; Field programmable gate arrays; Image edge detection; Monitoring; Simulation; Block Memory; FPGA; Sobel; VGA Interface;
Conference_Titel :
Emerging Trends in Communication, Control, Signal Processing & Computing Applications (C2SPCA), 2013 International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4799-1082-3
DOI :
10.1109/C2SPCA.2013.6749364
