Testable CMOS design for robust and logical testability of stuck-open/stuck-on faults

A novel robust testable CMOS design technique is proposed to detect all stuck-open and stuck-on faults by single test patterns for the logic circuit and two pattern sequences for the circuit added for testability. The proposed technique adds one transistor per gate for stuck-open fault testing and two transistors for stuck-on faults per gate or multi-level circuit. Thus, for multilevel circuits consisting of N gates, only N+2 additional transistors are required. The extra transistors for stuck-open faults are also capable of monitoring the output signals of gates, by which the observability of the circuit can be enhanced. The proposed technique uses single test patterns for the logic circuit, and hence the overall testing procedure and cost are significantly reduced