DocumentCode
3399254
Title
A redundant variable scaling CORDIC rotation engine implementation
Author
Harding, John A. ; Lang, Tomas
Author_Institution
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear
1991
fDate
14-17 May 1991
Firstpage
287
Abstract
The CMOS implementation of a high-performance rotation processor using redundant CORDIC is described in detail. This design replaces carry-propagate addition with carry-save addition, which is a fast form of parallel addition. Characteristics of 1.2-μm CMOS implementations are given
Keywords
CMOS integrated circuits; digital arithmetic; digital signal processing chips; parallel architectures; redundancy; signal processing; CMOS implementation; CORDIC rotation engine; carry-save addition; high-performance rotation processor; parallel addition; redundant variable scaling; Algorithm design and analysis; CMOS process; Computer architecture; Computer science; Digital arithmetic; Engines; Equations; Matrix decomposition; Parallel architectures; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-0620-1
Type
conf
DOI
10.1109/MWSCAS.1991.252043
Filename
252043
Link To Document