Non-classical scaling approaches for ultra deep sub micron technology

Technology scaling has been the workhorse of semiconductor industry for over three decades for achieving the goal of smaller, faster and cheaper ICs. But continuous scaling has led to decrease in feature sizes to such levels that the fundamental physical limits of materials have become a bottleneck for further miniaturization in the Ultra Deep Sub Micron regime. These limitations have posed a challenge in the form of short channel effects, off-state leakage current, gate leakage current, decrease in carrier mobility and on-state current, polysilicon depletion region and the effects of random dopant fluctuations. To counter these limitations, specific solutions have been critically examined and presented. These solutions mark the beginning of non-classical scaling era and include usage of strained silicon, high-k dielectrics, metal gate electrodes, exploration of other semiconductor materials and crystal orientations. Novel device architectures like Double Gate MOS, FinFET, MuGFET and Ultra Thin Body-Silicon on Insulator MOS are examined for their potential to keep Moore´s law alive for the next decade.