Title :
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost
Author :
Zhuang, Changwen ; Sakanushi, Keishi ; Jin, Liyan ; Kajitani, Yoji
Author_Institution :
Syst. Dev. Dept., SII EDA Technol. Inc., Fukuoka, Japan
Abstract :
This paper proposes a topological representation for the general floorplan, called the H-sequence, which can check channel-adjacency and boundary-adjacency in a constant time. Moreover, we define Routing-cost for the placement to measure its routing difficulty. Experimental results indicate that the H-sequence based placement algorithm can optimize routing-cost effectively in a short time.
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network routing; network topology; sequences; H-sequence; Q-sequence; VLSI floorplanning; boundary-adjacency; channel-adjacency optimization; placement; routing cost optimization; topological representation; Circuit synthesis; Cost function; Decoding; Electronic design automation and methodology; Pins; Routing; Semiconductor device measurement; Wire;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195038
