Non-slicing floorplans with boundary constraints using generalized Polish expression

In this paper, we address the problem of VLSI floorplanning, considering boundary constraints. The problem is practical and crucial in physical design, since architects decide to arrange some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. By using a new representation called the generalized Polish expression, we propose an efficient algorithm to handle the boundary constraints on non-slicing floorplans. In addition, a new fixing heuristic, based on modular similarity, is also presented to effectively fix the generated infeasible floorplans during the process. The experimental results are good in commonly used MCNC benchmark circuits.