Simulation study of Junctionless Vertical MOSFETS for analog applications

In this letter, we focus on the electrical characteristics of the Partially insulating oxide Junctionless Vertical MOSFET (Piox JLVFET) and Partially insulating oxide Junction Vertical MOSFET (Piox JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, whereas the PiOX JVFET needs an S/D implant. But, according to simulation results, we find out that the PiOX JVFET exhibits desired characteristics which are similar to those of the PiOX JLVFET. This means that the analog properties, such as gate transconductance (G_m), drain conductance (G_d) and intrinsic gain (A_v), can be almost the same for both devices. Additionally, the high S/D doping presented in the PiOX JVFET helps reduce the parasitic S/D resistance, resulting in an enhanced current drive. In other words, it is believed that based on the design requirements, the PiOX JVFET can still be considered as a candidate for future CMOS scaling.