DocumentCode
3399391
Title
Optimal reconfiguration sequence management [FPGA runtime reconfiguration]
Author
Ghiasi, Soheil ; Sarrafzadeh, Majid
Author_Institution
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
359
Lastpage
365
Abstract
In this paper, we present an efficient optimal algorithm for minimizing the runtime reconfiguration (context switching) delay of executing an application on a reconfigurable system. We assume that the basic operations of the application are already scheduled and each of them has to be realized on the reconfigurable fabric in order to be executed. The modeling and algorithm are both applicable to partially reconfigurable platforms as well as multi-FPGA systems. The algorithm can be directly applied to minimize the application runtime for many typical classes of applications, where the actual execution delay of basic operations is negligible compared to the reconfiguration delay. We prove the optimality and efficiency of our algorithm and report experimental results, which demonstrate 40% to 2.5% improvement in total runtime reconfiguration delay.
Keywords
circuit optimisation; field programmable gate arrays; logic design; minimisation; reconfigurable architectures; application execution delay; application runtime; basic operation execution delay; context switching; multi-FPGA systems; optimal reconfiguration sequence management; partial reconfiguration; partially reconfigurable platforms; reconfigurable hardware; reconfigurable system; reconfiguration delay; runtime reconfiguration minimization; Application software; Computer applications; Computer science; Delay effects; Field programmable gate arrays; Hardware; Process design; Processor scheduling; Runtime; Scheduling algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195041
Filename
1195041
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