Electrostatic discharge (ESD) and latchup in 3-D memory and system on chip applications

Author

Voldman, S.H.

Author_Institution

Dr. Steven H. Voldman LLC, South Burlington, VT, USA

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

Electrostatic discharge (ESD) protection and latchup issues in three dimensional (3-D) semiconductor chip systems is discussed for the first time. ESD protection in 3-D multi-chip systems will be important for both memory and system-on-chip (SOC) applications. Two types of 3-D semiconductor chips will be discussed; a first version introduces edge wiring, and a second version introduces through silicon vias (TSV). In this paper, a new memory device built using the first commercial CMOS manufacturing technology to employ TSVs will be discussed.

Keywords

electrostatic discharge; flip-flops; system-on-chip; three-dimensional integrated circuits; 3D memory; 3D multichip system; 3D semiconductor chip system; CMOS manufacturing technology; ESD protection; SOC application; TSV; edge wiring; eectrostatic discharge; latchup; memory device; silicon vias; system-on-chip; three dimensional semiconductor chip system; Capacitance; Electrostatic discharges; Pins; Silicon; Substrates; Through-silicon vias; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466748

Filename

6466748