Title :
The application of temporal logic for flexible scheduling within a high-level synthesis system
Author :
Beikzadeh, M.R. ; Mack, R.J.
Author_Institution :
Centre for VLSI Syst. Design, Essex Univ., Colchester, UK
Abstract :
An integrated approach for the automatic synthesis of a register transfer architecture from a behavioral description is presented. An internal representation is used based on modeling the temporal relationships between all operations in the specification. A two-phase design approach is presented: design pruning limits the design space through the application of design constraints while design selection produces a timing schedule meeting specific performance characteristics. The rule-based system described has been implemented in PROLOG on a Sun/4. The major advantage of the approach is its generality; unlike many systems, the design process does not operate in a fixed order but is flexible and constraint-oriented
Keywords :
PROLOG; expert systems; logic CAD; temporal logic; PROLOG; Sun/4; automatic synthesis; behavioral description; constraint-oriented; design constraints; design pruning; design selection; flexible scheduling; high-level synthesis system; integrated approach; register transfer architecture; rule-based system; temporal logic; timing schedule; two-phase design approach; Design methodology; Hardware; High level synthesis; Logic; Network synthesis; Pipelines; Process design; Processor scheduling; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.252069
