A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimation

Variable Block Size (VBS) motion estimation has been adopted by H.264/AVC for its compression efficiency and high video quality. In this paper we propose parallel 2-D architecture for computing the Motion Vectors (MV). This 2-D systolic array architecture is composed of 16 Processing Element (PE) with Carry Save Adder (CSA) compressor and comparators to compute Sum of Absolute Differences (SAD) of 4×4 macro block. By data reuse scheme using raster scan method the Sum of Absolute Difference (SAD) for variable blocks 8×4, 4×8, 8×8, 16×8, 8×16, 16×16 are computed from the SAD of 4×4 sub blocks resulting in 41 SADs. With the reduced computational complexity for the search range [16×16] our design operates at the frequency of 689.65MHz with the throughput of 43.1Mega blocks per second and the power dissipation is 246.13μW. Our design is synthesized by using Cadence RTL Compiler using TSMC 45nm CMOS technology with a gate count of 21.742k gates.