DocumentCode
3399860
Title
Design of a scalable RSA and ECC crypto-processor
Author
Sun, Ming-Cheng ; Su, Chih-Pin ; Huang, Chih-Tsun ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
495
Lastpage
498
Abstract
In this paper, we propose a scalable word-based crypto-processor that performs modular multiplication based on the modified Montgomery algorithm for finite fields GF(P) and GF(2m). The unified crypto-processor supports scalable keys of length up to 2048 bits for RSA and 512 bits for elliptic curve cryptography (ECC). Further extension of the key length can be done easily by enlarging the memory module or using the external memory resource. With the proposed parity prediction technique, our pipelined crypto-processor achieves a 512-bit RSA encryption rate of 276 kbps and a 160-bit ECC encryption rate of 73.3 kbps for a 220 MHz clock rate.
Keywords
integrated circuit design; integrated memory circuits; microprocessor chips; pipeline processing; public key cryptography; 160 bit; 2048 bit; 220 MHz; 276 Kbit/s; 512 bit; 73.3 Kbit/s; ECC encryption rate; RSA encryption rate; clock rate; elliptic curve cryptography; external memory resource; finite fields; key length; memory module; modified Montgomery algorithm; modular multiplication; parity prediction technique; pipelined crypto-processor; scalable RSA/ECC crypto-processor; scalable word-based crypto-processor design; unified crypto-processor; Application specific integrated circuits; Elliptic curve cryptography; Galois fields; Hardware; Iterative algorithms; Laboratories; Pipelines; Public key cryptography; Sun; Virtual private networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195066
Filename
1195066
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