Hierarchical layout synthesis of analogue VLSI circuits using an intelligent parsing mechanism

A hierarchical parsing technique for the layout synthesis of analog VLSI circuits is described. A technique by which the system makes use of the netlists contained in a knowledge database to generate the necessary program codes automatically is described. These codes forms a set of rules from which the layout corresponding to the input circuit description is synthesized. The unique feature of this approach is that these rules are automatically derived from the netlist, thereby eliminating the need for manual specification of rules, a process which is found to be tedious and highly error-prone