An efficient design technique of circular convolution circuit using Vedic Mathematics and McCMOS technique

This paper proposes a high speed low power circular convolution implementation of two finite length sequences by taking the advantage of fast Vedic Urdhva-Tiryakbhyam multiplication algorithm with a very efficient leakage control technique called Mutilple Channel CMOS (McCMOS) technique. The use of this Vedic formula allows for high speed convolution processing which happens frequently during the treatment of the time domain of signals. In this paper, the circular convolution is approached as a combination of Vedic multiplication unit and transmission gates based adders. The idea for designing the multiplication unit from Vedic Sutra is adopted because the partial sums and products are generated in only a single step. Furthermore McCMOS technique is used having non-minimum length transistors to offer the possibility of achieving excellent leakage control in nano-scale CMOS design with a very modest increase in area and switched capacitance. The simulations have been carried out in Cadence spice spectre using 130nm, 90nm, 65nm and 45nm node technology and presents comparative simulation results indicating the performance of the circuit. Thorough simulations show that the proposed architecture of designing the circular convolution achieves approximately 74-97% better performance in terms of PDP compared to the conventional architecture. The proposed technique will be very useful in different applications of time and space domains in digital image and signal processing.