Design of High-Speed-Pipelined Execution Unit of 32-bit RISC Processor

The paper describes the architecture and design of the pipelined execution unit of a 32-bit RISC processor. Organization of the blocks in different stages of pipeline is done in such a way that pipeline can be clocked at high frequency. Control and forward of `data flow´ among the stages are taken care by dedicated hardware logic. Different blocks of the execution unit and dependency among themselves are explained in details with the help of relevant block diagrams. The design has been modeled in verilog HDL and functional verification policies adopted for it have been described thoroughly. Synthesis of the design is carried out at 0.13-micron standard cell technology and for slow timing library the reported frequency of operation is 714 MHz at synthesis level