Investigating the performance of CNFET using 10T SET D-Flip flop

Author

Raguvaran, E. ; Vishnu, K.S.N. ; Chitra, S.H.

Author_Institution

Dept. of ECE, PSG Coll. of Technol., Coimbatore, India

fYear

2012

fDate

10-12 Jan. 2012

Firstpage

1

Lastpage

5

Abstract

This paper investigates the performance of Single Edge Triggered D-Flip flop (SET D-FF) using Carbon Nanotube Field Effect Transistors (CNFETs). The circuit performance of CNFET model has been compared with that of silicon based MOSFET model. CNFET circuit models are tested for various substrate bias voltages in sub threshold region. A 10 Transistor version of SET D-FF is implemented using PTM 32nm CMOS model and Stanford single-walled CNFET model and simulated using HSPICE. The performance parameter under investigation is Power Delay Product (PDP). The comparative simulation result at various frequencies show that CNFET SET DFFs have superior Power Delay Product over MOSFET SET DFFs.

Keywords

CMOS integrated circuits; carbon nanotube field effect transistors; flip-flops; C; CMOS model; CNFET circuit model; HSPICE; MOSFET model; PDP; SET D-FF; Stanford single-walled CNFET model; carbon nanotube field effect transistor; power delay product; single edge triggered D-flip flop; size 32 nm; substrate bias voltage; CNTFETs; Delay; Flip-flops; Integrated circuit modeling; MOSFET circuits; Semiconductor device modeling; CMOS; Carbon nano-tubes; MOSFET; PTM 32nm CMOS model; Power Delay Product (PDP); SET D-FF; Single Edge Triggered; Stanford single-walled CNFET model; Sub-threshold Region;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Communication and Informatics (ICCCI), 2012 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4577-1580-8

Type

conf

DOI

10.1109/ICCCI.2012.6158882

Filename

6158882