Test Vector Ordering For Power Reduction During Transmission of Compressed Test Patterns To Embedded System-On-Chip

Author

Giri, Chandan ; Cheruku, Nikhil Reddy ; Chattopadhyay, Santanu

Author_Institution

Dept. of Electr. & Electri.; & Comput. Eng., Indian Inst. of Technol., Kharagpur

fYear

2006

fDate

Sept. 2006

Firstpage

1

Lastpage

5

Abstract

This paper considers the problem of test-bus power reduction in system-on-chip testing. It has been seen that while the cores are fitted with P1500 wrapper, transitions occurring in the bypass registers can be comparable to those in the scan chain. Unlike bus encoding the proposed solution using test vector reordering does not use any extra hardware. It neither affects the compression ratio nor test application time. Experimental results on ISCAS89 benchmark circuits show up to 75% saving in flip count occurring in test bus in a dictionary based test data compression

Keywords

benchmark testing; data compression; integrated circuit testing; system-on-chip; ISCAS89 benchmark circuit; bus encoding; compressed test pattern; embedded system-on-chip; test vector reordering; test-bus power reduction; Automatic testing; Benchmark testing; Circuit testing; Decoding; Dictionaries; Energy consumption; Power dissipation; System testing; System-on-a-chip; Test data compression; Power optimization; System-On-Chip Testing; Test data compression; Test vector reordering;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference, 2006 Annual IEEE

Conference_Location

New Delhi

Print_ISBN

1-4244-0369-3

Electronic_ISBN

1-4244-0370-7

Type

conf

DOI

10.1109/INDCON.2006.302782

Filename

4086253