Microprocessor cache compressor design using P-Match algorithm

The speed of the microprocessors is being increasing faster than the speed of off-chip memory. When multiprocessors are used in the system design, more number of processors requires added accesses to memory. Accessing off-chip memory takes more time than accessing an on-chip cache, and some more time to execute an instruction. Cache compression presents the confront that the processor speed has to be improved but it should not substantially increase the total chip power consumption. This architecture has number of new features adapted for the application. In the proposed work if there are consecutive zero´s or one´s then there patterns are encoded and the dictionary matching is bypassed. By this method the speed and the power can be improved without affecting the performance of the system cache.