MAPLE chip: a processing element for a static scheduling centric multiprocessor

Author

Yasufuku, Kenta ; Ogawa, Riku ; Iwai, Keisuke ; Amano, Hideharu

Author_Institution

Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

575

Lastpage

576

Abstract

A custom processor called MAPLE, which supports static scheduling by automatic parallelizing compilers, is implemented and evaluated. MAPLE has a high performance floating point arithmetic unit and low latency data transfer mechanism for other MAPLE chips. The maximum operational frequency is 80 MHz in simulation, and the operation on the prototype board with 23 MHz clock is confirmed. It requires about 0.56 W at 23 MHz operation.

Keywords

floating point arithmetic; integrated circuit design; logic design; microprocessor chips; multiprocessing systems; parallelising compilers; processor scheduling; reduced instruction set computing; 0.56 W; 23 MHz; 32 bit; 80 MHz; MAPLE; RISC processor; advanced scheduling oriented computer architecture; automatic parallelizing compilers; floating point arithmetic unit; low latency data transfer mechanism; maximum operational frequency; multiprocessor system ASCA processing element; static scheduling centric multiprocessor; CMOS technology; Clocks; Computer science; Frequency; Packaging; Parallel processing; Pipelines; Processor scheduling; Prototypes; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195085

Filename

1195085