Design of online testable fast divider

Division is the critical arithmetic operation for high speed digital design like 3-D graphics and DSP applications. Faster the arithmetic operation so is the application and power efficiency of such operations leads to durability of the system. But VLSI implementation of division is generally slower and more area consuming than the other three basic arithmetic operations such as addition, subtraction and multiplication. Owing to its advantages over PTL, CMOS logic based divider proves 92% faster and 99% power efficient with 25% area overhead. Also the complexity of the divider circuit causes its testing a bottleneck to system testing. Here we propose optimized non-restoring division algorithm with remainder decoding using CMOS logic in 90nm technology. Also we demonstrate the application of BIST to larger divider circuit. We compare the use of conventional LFSR and Cellular Automation for PRPG. And for output compression and signature analysis MISRs seem to be very effective due to their less area overhead.