Hardware implementation of an EAN-13 bar code decoder

Author

De Maeyer, Jeroen ; Devos, Harald ; Meeus, Wim ; Verplaetse, Peter ; Stroobandt, Dirk

Author_Institution

Ghent Univ., Gent, Belgium

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

583

Lastpage

584

Abstract

This paper presents an FPGA hardware implementation of a bar code decoder using the EAN-13 standard. The design was implemented on an FPGA situated on an ATMEL FPLSIC (field programmable system level integrated circuit, AT94K40-25DQC). The design has comparable performance and is in many ways more robust than commercially available devices. However, to the authors´ knowledge, these all use a microprocessor while our design is purely dedicated hardware.

Keywords

bar codes; code standards; decoding; field programmable gate arrays; logic design; AT94K40-25DQC; EAN-13 standard; FPGA; FPLSIC; bar code decoder; field programmable system level integrated circuit; hardware implementation; Bars; Code standards; Decoding; Encoding; Europe; Field programmable gate arrays; Flowcharts; Hardware; Optical reflection; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195089

Filename

1195089

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3400308