Title :
Design of a digital CDMA receiver
Abstract :
In this work, an attempt has been made to design a digital signal code division multiple access receiver using VHDL and synthesize it using Mentor Graphics tools. The receiver is designed for a maximum of three users, as per the design specification given for the contest. The novelty of this design is that it uses four independent processes to achieve the concurrent operation for the entire functionality. The simulation and synthesis are carried out using Mentor Graphics´ FPGA tools and an optimized circuit in terms of area and timing is generated.
Keywords :
circuit optimisation; code division multiple access; field programmable gate arrays; hardware description languages; logic CAD; radio receivers; FPGA; VHDL; circuit area; circuit optimization; circuit timing; digital CDMA receiver; digital signal code division multiple access receiver; independent process concurrent operation; maximum user number; Clocks; Counting circuits; Information technology; Multiaccess communication; Signal design; Signal generators; Signal processing; Signal synthesis; Synchronous generators; Transmitters;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195091
