Design of a digital CDMA receiver

In this work, an attempt has been made to design a digital signal code division multiple access receiver using VHDL and synthesize it using Mentor Graphics tools. The receiver is designed for a maximum of three users, as per the design specification given for the contest. The novelty of this design is that it uses four independent processes to achieve the concurrent operation for the entire functionality. The simulation and synthesis are carried out using Mentor Graphics´ FPGA tools and an optimized circuit in terms of area and timing is generated.