Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies

Author

Hashimoto, Masanori ; Fujimori, Kazunori ; Onodera, Hidetoshi

Author_Institution

Dept. Commun. & Comput. Eng., Kyoto Univ., Japan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

589

Lastpage

590

Abstract

We developed standard cell libraries for three technologies (0.13, 0.18 and 0.35 μm) using an automatic layout generation tool that we have developed. The developed libraries are as competitive as manually-designed libraries in layout density and speed. We verify the functionalities of all cells and the speed of basic combinational cells on fabricated chips. The libraries are currently public to educational organizations in Japan.

Keywords

circuit CAD; combinational circuits; integrated circuit layout; libraries; logic CAD; 0.13 micron; 0.18 micron; 0.35 micron; automatic layout generation tool; cell driving strength; cell functionality verification; combinational cell speed; driving strength variation; fabrication process technologies; layout density; layout speed; logical functions; publicly available cell libraries; standard cell libraries; Application specific integrated circuits; Delay; Design methodology; Design optimization; Libraries; MOS devices; Mesh generation; Semiconductor device measurement; Standards development; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195092

Filename

1195092