Title :
IBM´s 50 million gate ASICs
Author :
Koehl, Juergen ; Lackey, David E. ; Doerre, George
Author_Institution :
IBM Microeletronics, Essex Junction, VT, USA
Abstract :
There is no slowdown in the complexity increase for ASIC and SoC designs. As we write this paper in August, 2002, 40 M gate ASICs are nearing tape-out, and 50 M gate designs are likely to start before this conference takes place. This paper describes the current tool and methodology development efforts focused on enabling ASIC and SoC designs of these sizes and complexity, centered around the reduction of design turn-around-time, improvement of the quality of results and the modeling and optimization of deep sub-micron electrical effects.
Keywords :
application specific integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; logic design; system-on-chip; ASIC complexity; SoC design; chip gate count; chip size; circuit modeling; circuit reuse; design methodologies; design tools; design turn-around-time reduction; optimization; quality improvement; sub-micron electrical effects; Algorithm design and analysis; Amplitude shift keying; Application specific integrated circuits; Chip scale packaging; Design optimization; Hardware; Logic; Microelectronics; Rivers; Timing;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195100
