DocumentCode :
3400881
Title :
On effective criterion of path selection for delay testing
Author :
Fukunaga, Masayasu ; Kajihara, Seiji ; Takeoka, Sadami ; Yosimura, Shinichi
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan
fYear :
2003
fDate :
21-24 Jan. 2003
Firstpage :
757
Lastpage :
762
Abstract :
Since a logic circuit often has too many paths to test delay all paths in the circuit, it is necessary for path delay testing to limit the number of paths to be tested. Paths to be tested should be ones with large delay that are more likely to cause a fault. In addition, a test set for the paths are required to detect as many as possible other models of faults. In this paper, we investigate criteria of path selection for path delay testing. We first define two typical criteria to be investigated here, and then experimentally show the features of paths selected with each criterion, with respect to fault coverage of other delay fault models. From our experiments, we observe that test patterns for the longest paths cannot cover many other faults such as gate delay faults or segment delay faults.
Keywords :
automatic test pattern generation; fault location; integrated circuit modelling; integrated circuit testing; logic testing; delay fault models; fault coverage; fault detection models; gate delay faults; logic circuit test; path delay testing; path selection criteria; path test set; segment delay faults; test patterns; tested path limitation; Circuit faults; Circuit testing; Computer science; Delay effects; Electrical fault detection; Fault detection; Logic testing; Propagation delay; Test pattern generators; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
Type :
conf
DOI :
10.1109/ASPDAC.2003.1195121
Filename :
1195121
Link To Document :
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