Title :
The VLSI implementation of a square root algorithm
Author :
Bannur, J. ; Varma, A.
Author_Institution :
Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA 00089
Abstract :
VLSI implementation of a square root algorithm is studied. Two possible implementations of the basic non-restoring algorithm are presented — the second is more area-efficient and modular than the first. The implementations are simple and easy to control, but, at the same time, are more area-time efficient than many existing designs. A hardware algorithm suited to microprogram implementation is also given. Extension of the algorithms to achieve ½ bit precision is discussed.
Keywords :
Adders; Algorithm design and analysis; Clocks; Flip-flops; Hardware; Registers; Very large scale integration;
Conference_Titel :
Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
Conference_Location :
Urbana, IL,
DOI :
10.1109/ARITH.1985.6158929
