Title :
Highly scalable algorithms for rectilinear and octilinear Steiner trees
Author :
Kahng, Andrew B. ; Mãndoiu, Ion I. ; Zelikovsky, Alexander Z.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, CA, USA
Abstract :
The rectilinear Steiner minimum tree (RSMT) problem, which asks for a minimum-length interconnection of a given set of terminals in the rectilinear plane, is one of the fundamental problems in electronic design automation. Recently there has been renewed interest in this problem due to the need for highly scalable algorithms able to handle nets with tens of thousands of terminals. In this paper we give a practical O(n log2 n) heuristic for computing near-optimal rectilinear Steiner trees based on a hatched version of the greedy triple contraction algorithm of Zelikovsky (Algorithmica vol. 9, pp. 463-470, 1993). Experiments conducted on both random and industry test cases show that our heuristic matches or exceeds the quality of best known RSMT heuristics, e.g. on random instances with more than 100 terminals our heuristic improves over the rectilinear minimum spanning tree by an average of 11%. Moreover, our heuristic has very good runtime scaling, e.g. it can route a 34k-terminals net extracted from a real design in less than 25 seconds compared to over 86 minutes needed by the O(n2) edge-based heuristic of Borah, Owens, and Irwin (Discrete Appl. Math. vol. 90, pp. 51-67, 1999). Since our heuristic is graph-based, it can be easily modified to handle practical considerations such as routing obstacles, preferred directions, via costs, and octilinear routing - indeed, experimental results show only a small factor increase in runtime when switching from rectilinear to octilinear routing.
Keywords :
VLSI; algorithm theory; circuit layout CAD; integrated circuit layout; network routing; network topology; trees (mathematics); 25 s; 86 min; RSMT; RSMT heuristics; edge-based heuristic; electronic design automation; graph-based heuristic; greedy triple contraction algorithm; minimum-length interconnection; net routing time; octilinear Steiner trees; octilinear routing; preferred directions; rectilinear Steiner minimum tree problem; rectilinear Steiner trees; rectilinear minimum spanning tree; rectilinear plane terminals; rectilinear routing; routing obstacles; runtime scaling; scalable algorithms; via costs; Computer science; Costs; Electronic design automation and methodology; Research and development; Routing; Runtime; Silicon; Steiner trees; Testing; Tree graphs;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195132