• DocumentCode
    3401129
  • Title

    PAPIA: Pyramidal architecture for parallel image analysis

  • Author

    Cantoni, V. ; Ferretti, M. ; Levialdi, S. ; Stefanelli, R.

  • Author_Institution
    Department of Computer and System Science - Universita di Pavia, Strada Nuova 106/c - 27100 Pavia - Italy
  • fYear
    1985
  • fDate
    4-6 June 1985
  • Firstpage
    237
  • Lastpage
    242
  • Abstract
    In 1981 a national research program for the design, simulation and construction of a multiprocessor image processing system was started. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks and to the evaluation of the performances of the major classes of machines, a new system has been defined. The structure of the new system is based on a pyramid of processors and many applications in which this machine may be exploited are highlighted. The multiprocessor architecture has been fully designed and the chip will be built by an Italian silicon. foundry, the SGS company, within the framework of the multichip national project.
  • Keywords
    Arrays; Image processing; Pins; Program processors; Shift registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
  • Conference_Location
    Urbana, IL,
  • Type

    conf

  • DOI
    10.1109/ARITH.1985.6158932
  • Filename
    6158932