Algorithm partition for a fixed-size VLSI architecture using space-time domain expansion

The space-time domain expansion method has recently been used to transform a computational task with a recursive formula into a VLSI architecture. In addition to its simplicity and completeness, an important advantage of this method is that it can easily solve the problem of partitioning an algorithm to fit a fixed size VLSI architecture. We propose a computational model and a partition rule which can be easily used to partition any recursive computation problem suited to the space-time domain expansion method so it can be solved on fixed-size VLSI architectures. Several examples, such as partitioned vector inner product, partitioned comparators in relational database management, partitioned matrix multiplications, and partitioned transitive closure computation, parallel recognition of general context-free languages, string matching and dynamic time-warp pattern-matching are used to illustrate the proposed method.