• DocumentCode
    3401259
  • Title

    Efficient serial-parallel arrays for multiplication and addition

  • Author

    Cirainiera, L. ; Serra, A.

  • Author_Institution
    Dipartimento di Automatica e Informatica - Politecnico di Torino-Torino, Italy
  • fYear
    1985
  • fDate
    4-6 June 1985
  • Firstpage
    28
  • Lastpage
    35
  • Abstract
    Three new arrays for unsigned and signed multiplication, and for multiplication/addition are presented. It is assumed that the factors are axpressed in 2´s complement, while the addend (in the latter array only) and the result are expressed in a redundant notation. The arrays operate in serial-parallel way, since one factor is input in parallel, while the second factor and the addend (in the case of multiplication/addition) are entered digit by digit starting from the most significant one; the result is also produced serially with the most significant digit first. Hence, the arithmetic unit presented is suitable to be used as basic block of special purpose processors performing functions such as non-recursive digital filtering, signal correlation and matrix multiplication. Indeed, they have the same speed improvements as other similar units using redundant representations for the result, with a cost equivalent to their counterparts based on full 2´s complement representation.
  • Keywords
    Adders; Clocks; Delay; Equations; Kernel; Logic gates; Program processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
  • Conference_Location
    Urbana, IL,
  • Type

    conf

  • DOI
    10.1109/ARITH.1985.6158937
  • Filename
    6158937