Learning To Optimize VLSI Design Problems

We show applications of a new global optimization strategy that combines support vector machine (SVM) learning with simple local search. The use of SVM learning allows prediction of locations of the global optimum from knowledge of a few local minima. This is particularly valuable in VLSI design applications, where the search space is extremely large. The approach does not need the cost function or constraints to be provided in analytical form, thus allowing the optimizer to be linked with a circuit simulator that provides highly accurate information about circuit behavior. Experimental results show that the optimizer is highly effective in sizing transistors in analog CMOS circuits