Title :
A multioperand two´s complement addition algorithm
Author :
Kobayashi, Hideaki
Author_Institution :
Department of Electrical and Computer Engineering University of South Carolina Columbia, SC 29208
Abstract :
This paper presents a novel algorithm for summing a set of 2´s complement numbers in parallel. The 2´s complement addition is converted to an equivalent parallel summation of unsigned numbers. The conversion is performed by simply complementing all the sign bits. Only a few constant bits are required for sign correction. This algorithm is suitable for computer-aided design (CAD) of custom VLSI.
Keywords :
Adders; Algorithm design and analysis; Computers; Design automation; Layout; Logic gates; Very large scale integration;
Conference_Titel :
Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
Conference_Location :
Urbana, IL,
DOI :
10.1109/ARITH.1985.6158958
