Design and FPGA implementation of a Viterbi decoder: A case study using SystemVerilog and co-simulation

Author

Tang, Jiuling

Author_Institution

Dept. of Electr. Eng., Univ. of Windsor, Windsor, ON, Canada

fYear

2009

fDate

14-17 Dec. 2009

Firstpage

1

Lastpage

6

Abstract

Design and field programmable gate array (FPGA) implementation of a high-speed Viterbi decoder with a constraint length of 7 and a code rate of 1/2 is presented here. Based on an algorithmic state machine (ASM) flowchart of Viterbi algorithm and by taking advantages of lookup tables and parallelism, this hard-decision decoder has a throughput of 510 Mbps. Its RTL code and self-checking test bench are all written in SystemVerilog. The code is functionally verified in various situations, including several directed test cases and numerous random test cases. It is also verified in the Simulink and ModelSim co-simulation environment. The FPGA implementation results show that its core can run as high as 510 MHz, and has 80.39 ns latency.

Keywords

Viterbi decoding; field programmable gate arrays; hardware description languages; table lookup; FPGA implementation; ModelSim co-simulation; RTL code; Simulink; SystemVerilog; algorithmic state machine flowchart; field programmable gate array; hard decision decoder; high-speed Viterbi decoder; lookup tables; self checking test bench; Channel capacity; Convolutional codes; Error correction; Field programmable gate arrays; Forward error correction; Maximum likelihood decoding; Testing; Throughput; Viterbi algorithm; Wireless communication; Co-simulation; Convolutional encoder; FPGA; SystemVerilog; Viterbi decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Information Technology (ISSPIT), 2009 IEEE International Symposium on

Conference_Location

Ajman

Print_ISBN

978-1-4244-5949-0

Type

conf

DOI

10.1109/ISSPIT.2009.5407512

Filename

5407512