Generating compact assertions for control-based logic signals

This paper presents two approaches for writing compact sets of assertions and for gauging the level of coverage in the assertions. We present a state-table method for writing control-based assertions containing only the necessary Boolean conditions that affect a given control signal. An assertion coverage analyzer was developed to measure the attained assertion coverage based on a set of verification test sequences. Combining both of our methods enables verifiers to measure the quality of their written assertions, which can then be used in formal or dynamic verification. The circuit designs used show that our approach is able to generate additional compact assertions and achieve improved assertion coverage.