DocumentCode
3401811
Title
A 45nm SOI-CMOS PLL with a wideband LC-VCO
Author
Kun-Seok Lee ; Sungho Beck ; Hamhee Jeon ; Youngchang Yoon ; Jaehyouk Choi ; Chang-Ho Lee ; Kenney, J.
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2011
fDate
7-10 Aug. 2011
Firstpage
1
Lastpage
4
Abstract
A 45nm SOI-CMOS PLL with a wideband LC-VCO is presented. The proposed PLL uses the advantage of SOI technology such as small parasitic capacitance and high Q-factor. The frequency range of the PLL is maximized because of a high maximum-to-minimum capacitance ratio of a capacitor bank. Measurement results show that the VCO generates 4.87-to-9.65GHz frequency signals with 65.8% frequency coverage. Fabricated chip occupies 0.09mm2 of active area and consumes less than 7mA current from single 1.0V supply.
Keywords
CMOS integrated circuits; Q-factor; phase locked loops; silicon-on-insulator; voltage-controlled oscillators; Q-factor; SOI-CMOS PLL; maximum-minimum capacitance ratio; parasitic capacitance; size 45 nm; voltage 1 V; wideband LC-VCO; CMOS integrated circuits; CMOS technology; Capacitors; MOS devices; Phase locked loops; Switches; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location
Seoul
ISSN
1548-3746
Print_ISBN
978-1-61284-856-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2011.6026273
Filename
6026273
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